1. Field of the Invention
The present invention relates to a multi-gate transistor having a gate electrode with improved performance and a fabrication method thereof.
2. Description of the Related Art
Multi-gate transistors having a double-gate structure or a tri-gate structure have been developed for next-generation devices. These devices overcome degradation of performance due to a reduction of gate length (Lg) accompanied with scale down in devices (Kunihiro Suzuki et al., IEEE 1993 “Scaling Theory for Double-Gate SOI MOSFETs”; Robert Chau, SSDM 2002, “Advanced Depleted-Substrate Transistors: Single-Gate, Double-Gate and Tri-Gate”; Z. Krivokapic, SSDM 2003, “High Performance 45 nm CMOS Technology with 20 nm Multi-Gate Devices”; Jeong-Hwan Yang, IEDM 2003, “Fully Working 6T-SRAM Cell with 45 nm Gate Length Triple Gate Transistors”).
A multi-gate transistor having a double-gate or tri-gate structure has a higher tolerance on the thickness (Tsi) of a fully depleted region compared with a single-gate transistor.
Such a general multi-gate transistor structure includes an active pattern formed by patterning a single crystalline silicon body on an insulating layer of a silicon-on-insulator (SOI) wafer and a gate electrode formed on a side and/or an upper surface of the active pattern.
To fabricate a conventional multi-gate transistor an active pattern is formed by patterning a silicon body formed on an insulating layer. Polysilicon for forming a gate electrode is deposited on a lateral surface and/or an upper surface of the active pattern. Here, the underlying active pattern makes the entire surface of polysilicon deposited uneven. Thus, it is quite difficult to perform a photolithography process for forming the gate electrode. To solve this problem, a planarizing process using chemical mechanical polishing (CMP) is additionally performed after depositing a thick layer of polysilicon.
However, in depositing the polysilicon, the thickness of polysilicon deposited is not uniform, resulting in a deviation in the thickness of polysilicon deposited throughout the surface. In the CMP process based on time control, a deviation in the thickness of polysilicon polished throughout the surface may also be generated. The deviation in the thickness of polysilicon makes it difficult to control the thickness of the gate electrode. For example, when it is intended to deposit polysilicon to a thickness of several hundreds to several thousands of Angstroms, use of conventional CMP may cause a thickness deviation of several hundred angstroms across the surface of deposited polysilicon. Thus, it is difficult to control the thickness of a gate electrode structure, ultimately resulting in a degradation of electrical characteristics of the transistor.